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Freescale Semiconductor /MK61F15WS /DDR /CR03

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Interpret as CR03

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)LATLIN0RESERVED 0LATGATE0RESERVED 0WRLAT0RESERVED 0TCCD0RESERVED

LATLIN=0000

Description

DDR Control Register 3

Fields

LATLIN

Latency Linear

0 (0000): Reserved

1 (0001): Reserved

2 (0010): 1 cycle

3 (0011): 1.5 cycles

15 (1111): 7.5 cycles
RESERVED

Reserved
LATGATE

Latency Gate
RESERVED

Reserved
WRLAT

Write Latency
RESERVED

Reserved
TCCD

Time CAS-to-CAS Delay
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data